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(R)
NO R
May 2001
DUCT E PR O MENT SOLET D REPL ACE OB E MEND EC O M
ICM7224
4 1/2 Digit LCD Display Counter
Description
The ICM7224 device is a high-performance, CMOS 41/2 digit counter, including decoder, output latch, display driver, count inhibit, leading zero blanking, and reset circuitry. The counter section provides direct static counting, guaranteed from DC to 15MHz, using a 5V 10% supply over the operating temperature range. At normal ambient temperatures, the devices will typically count up to 25MHz. The COUNT input is provided with a Schmitt trigger to allow operation in noisy environments and correct counting with slowly changing inputs. The COUNT INHIBIT, STORE and RESET inputs allow a direct interface with the ICM7207 and ICM7207A to implement a low cost, low power frequency counter with a minimum component count. These devices also incorporate several features intended to simplify cascading four-digit blocks. The CARRY output allows the counter to be cascaded, while the Leading Zero Blanking INput and OUTput allows correct Leading Zero Blanking between four-decade blocks. The BackPlane driver of the LCD devices may be disabled, allowing the segments to be slaved to another backplane signal, necessary when using an eight or twelve digit, single backplane display. These devices provide maximum count of 19999. The display drivers are not of the multiplexed type and each display segment has its own individual drive pin, providing high quality display outputs.
Features
* High Frequency Counting - Guaranteed 15MHz, Typically 25MHz at 5V * Low Power Operation - Typically Less Than 100W Quiescent * STORE and RESET Inputs Permit Operation as Frequency or Period Counter * True COUNT INHIBIT Disables First Counter Stage * CARRY Output for Cascading Four-Digit Blocks * Schmitt-Trigger on the COUNT Input Allows Operation in Noisy Environments or with Slowly Changing Inputs * Leading Zero Blanking INput and OUTput for Correct Leading Zero Blanking with Cascaded Devices * Provides Complete Onboard Oscillator and Divider Chain to Generate Backplane Frequency, or Backplane Driver May be Disabled Allowing Segments to be Slaved to a Master Backplane Signal
Pinout
ICM7224 (PDIP) TOP VIEW
VDD E1 G1 F1 BP A2 B2 C2 D2 E2 G2 F2 A3 B3 C3 D3 E3 G3 F3 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 D1 39 C1 38 B1 37 A1 36 OSCILLATOR 35 VSS 34 STORE 33 RESET 32 COUNT 31 COUNT INHIBIT 30 LZB OUT 29 LZB IN 28 CARRY 27 1/2 - DIGIT 26 F4 25 G4 24 E4 23 D4 22 C4 21 B4
Part Number Information
PART NUMBER ICM7224IPL TEMP. RANGE ( oC) -25 to 85 PACKAGE 40 Ld PDIP PKG. NO. E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
File Number
3168.2
1
ICM7224 Functional Block Diagram
LSD DIGIT 1 SEGMENT OUTPUTS DIGIT 2 SEGMENT OUTPUTS DIGIT 3 SEGMENT OUTPUTS DIGIT 4 SEGMENT OUTPUTS
1/ DIGIT 2
MSD
OUTPUT
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
1/ DIGIT 2
DRIVER
STORE
7 WIDE LATCH
7 WIDE LATCH
7 WIDE LATCH
7 WIDE LATCH
1/ DIGIT 2
LATCH
LEADING ZERO BLANKING OUTPUT COUNT INHIBIT COUNT INPUT RESET SCHMITT TRIGGER
DECODER
DECODER
DECODER
DECODER VDD
LEADING ZERO BLANKING INPUT Q 1/ 2
CL R
/2
Q
CL
/5
R
Q
CL R
/2
Q
CL
/5
R
Q
CL R
/2
Q
CL
/5
R
Q
CL R
/2
Q
CL
/5
R
D
Q
DIGIT CL R CARRY OUTPUT
OSCILLATOR INPUT
OSCILLATOR
+124
BLACKPLANE DRIVER ENABLE
BP INPUT/OUTPUT
ENABLE DETECTOR
2
ICM7224
Absolute Maximum Ratings
Supply Voltage (V DD - VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage (Any Terminal) (Note 1) . . . (VDD + 0.3V) to (VSS - 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from sources operating on a different power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7224 be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Operating Current, IDD Operating Supply Voltage Range (VDD - VSS), VSUPPLY
VDD = 5V, VSS = 0V, TA = 25oC, Unless Otherwise Indicated TEST CONDITIONS Test Circuit, Display Blank MIN 3 Pin 36 CLOAD = 200pF CLOAD = 5000pF Pin 36 Floating Pin 36 Floating Pins 29, 31, 33, 34, VIN = VDD - 3V Pins 29, 31, 33, 34 Pins 29, 31, 33, 34 3 CARRY Pin 28 Leading Zero Blanking OUT Pin 30 VOUT = VDD - 3V CARRY Pin 28 Leading Zero Blanking OUT Pin 30 VOUT = +3V 4.5V < VDD < 6V -350 TYP 10 2 0.5 1.5 19 150 10 2 0.5 -500 MAX 50 6 10 1 UNIT A V A s s kHz Hz A V V V V A
OSClLLATOR Input Current, IOSCI Segment Rise/Fall Time, tr , tf BackPlane Rise/Fall Time, tr , tf Oscillator Frequency, fOSC Backplane Frequency, fBP Input Pullup Currents, IP Input High Voltage, VIH Input Low Voltage, VIL COUNT Input Threshold, V CT COUNT Input Hysteresis, VCH Output High Current, IOH
Output Low Current, IOL
350
500
-
A
Count Frequency, fCOUNT STORE, RESET Minimum Pulse Width, tS , tr
0 3
-
15 -
MHz s
Timing Waveforms
OSCILLATOR FREQUENCY 128 CYCLES BACKPLANE INPUT/OUTPUT OFF SEGMENTS 64 CYCLES 64 CYCLES
ON SEGMENTS
FIGURE 1. ICM7224 DISPLAY WAVEFORMS
3
ICM7224 Typical Performance Curves
30 25 SUPPLY CURRENT (A) 20 15 10 5 0 TA = 70oC LCD DEVICES, TEST CIRCUIT DISPLAY BLANK PIN 36 OPEN 1000 LCD DEVICES TA = 25oC VSUPPLY = 5V
BP = OSC HZ
TA = -20oC
100
TA = 25oC
128
VSUPPLY = 6V
10
VSUPPLY = 4V VSUPPLY = 3V
1
2
3 4 5 SUPPLY VOLTAGE (V)
6
7
1
1
10 COSC (pF)
100
1000
FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE
FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF OSCILLATOR CAPACITOR COSC
45 40 35 30 25 20 15 SINE WAVE INPUT SWINGING FULL SUPPLY TA = -20 oC TA = 25oC TA = 70oC SUPPLY CURRENT (mA)
10 V+ = 5V TA = 25 oC 1
MAX (MHz)
0.1
4
5 SUPPLY VOLTAGE (V)
6
0.01 1kHz
10kHz
100kHz
1MHz
10MHz
100MHz
COUNT FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF COUNT FREQUENCY
FIGURE 4. MAXIMUM COUNT FREQUENCY (TYPICAL) AS A FUNCTION OF SUPPLY VOLTAGE
TABLE 1. CONTROL INPUT DEFINITIONS TERMINAL 29 INPUT Leading Zero Blanking INput 31 COUNT INHIBIT VOLTAGE VDD or Floating VSS VDD or Floating VSS 33 RESET VDD or Floating VSS 34 STORE VDD or Floating VSS FUNCTION Leading Zero Blanking Enabled Leading Zeroes Displayed Counter Enabled Counter Disabled Inactive Counter Reset to 0000 Output Latches not Updated Output Latches Updated
4
ICM7224 Control Input Definitions
In Table 1, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are specified in the Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. disabled during the negative portion of the overdriving signal (which could cause a DC component to the display). This can be done by driving the OSCILLATOR input between the positive supply and a level out of the range where the backplane disable is sensed, about one fifth of the supply voltage above the negative supply. Another technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsecond. The backplane disable sensing circuit will not respond to signals of this duration.
Detailed Description
The ICM7224 provides outputs suitable for driving conventional 41/2 digit by seven segment LCD displays. It includes 29 individual segment drivers, a backplane driver, and a selfcontained oscillator and divider chain to generate the backplane frequency (See Functional Block Diagram). The segment and backplane drivers each consist of a CMOS inverter, with the N-Channel and P-Channel devices ratioed to provide identical on resistances, and thus equal rise and fall times. This eliminates any DC component which could arise from differing rise and fall times, and ensures maximum display life. The backplane output can be disabled by connecting the OSCILLATOR input (pin 36) to VSS . This synchronizes the 29 segment outputs directly with a signal input at the BP terminal (pin 5) and allows cascading of several slave devices to the backplane output of one master device. The backplane may also be derived from an external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave device will represent a load of approximately 200pF (comparable to one additional segment). The limitation on the number of devices that can be slaved to one master device backplane driver is the additional load represented by the larger backplane of displays of more than four digits, and the effect of that load on the backplane rise and fall times. A good rule of thumb to observe in order to minimize power consumption, is to keep the rise and fall times less than about 5 microseconds. The backplane driver of one device should handle the back-plane to a display of 16 one-half-inch characters without the rise and fall times exceeding 5s (i.e., 3 slave devices and the display backplane driven by a fourth master device). It is recommended that if more than four devices are to be slaved together, that the backplane signal be derived externally and all the lCM7224 devices be slaved to it. This external backplane signal should be capable of driving very large capacitive loads with short (1-2s) rise and fall times. The maximum frequency for a backplane signal should be about 150Hz, although this may be too fast for optimum display response at lower display temperatures, depending on the display used. The onboard oscillator is designed to free run at approximately 19kHz, at microampere power levels. The oscillator frequency is divided by 126 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running. The oscillator frequency may be reduced by connecting an external capacitor between the OSCillator terminal (pin 36) and VDD; see the plot of oscillator/back-plane frequency in "Typical Performance Curves" for detailed information. The oscillator may also be overdriven if desired, although care must be taken to insure that the backplane driver is not
Counter Section
The lCM7224 implements a four-digit ripple carry resettable counter, including a Schmitt trigger on the COUNT input and a CARRY output. Also included is an extra D-type flip-flop, clocked by the CARRY signal which controls the half-digit segment driver. This output driver can be used as either a true half-digit or as an overflow indicator. The counter will increment on the negative-going edge of the signal at the COUNT input, while the CARRY output provides a negativegoing edge following the count which increments the counter from 9999 to 10000. Once the half-digit flip-flop has been clocked, it can only be reset (with the rest of the counter) by a negative level at the RESET terminal, pin 33. However, the four decades will continue to count in a normal fashion after the half-digit is set, and subsequent CARRY outputs will not be affected. A negative level at the COUNT INHIBIT input disables the first divide-by-two in the counter chain without affecting its clock. This provides a true inhibit, not sensitive to the state of the COUNT input, which prevents false counts that can result from using a normal logic gate to prevent counting. Each decade of the counter directly drives a four-to-seven segment decoder which develops the required output data. The output data is latched at the driver. When the STORE pin is low, these latches are updated, and when it is high or floating, the latches hold their contents. The decoders also include zero detect and blanking logic to provide leading zero blanking. When the Leading Zero Blanking INput is floating or at a positive level, this circuitry is enabled and the device will blank leading zeroes. When it is low, or the half-digit is set, leading zero blanking is inhibited, and zeroes in the four digits will be displayed. The Leading Zero Blanking OUTput is provided to allow cascaded devices to blank leading zeroes correctly. This output will assume a positive level only when all four digits are blanked; this can only occur when the Leading Zero Blanking INput is at a positive level and the half-digit is not set. For example, in an eight-decade counter with overflow using two lCM7224 devices, the Leading Zero Blanking OUTput of the high order digit would be connected to the Leading Zero Blanking INput of the low order digit device. This will assure correct leading zero blanking for all eight digits. The STORE, RESET, COUNT INHIBIT, and Leading Zero Blanking INputs are provided with pullup devices, so that they may be left open when a positive level is desired. The CARRY and Leading Zero Blanking OUTputs are suitable for
5
ICM7224
interfacing to CMOS logic in general, and are specifically designed to allow cascading of the devices in four-digit blocks.
Applications
Figure 8 shows an 8-digit precision frequency counter. The circuit uses two ICM7224s cascaded to provide an 8-digit display. Backplane output of the second device is disabled and is driven by the first device. The 1/2 digit output of the second device is used for overflow indication. The input signal is fed to the first device and the COUNT input of the second is driven by the CARRY output of the first. Notice that leading zero blanking is controlled on the second device and the LZB OUT of the second one is tied to LZB IN of the first one. An ICM7207A device is used as a timebase generator and frequency counter controller. It generates count window, store and reset signals which are directly compatible with ICM7224 inputs (notice the need for an inverter at COUNT INHIBIT input). The ICM7207A provides two count window signals (1s and 0.1s gating) for displaying frequencies in Hz or tens of Hz (x10Hz).
5V
a f g e d c
DP
b
+
-
200pF
1 VDD 2 3 ICM7224
40 39 38 37 OSCILLATOR 36 VSS 35 STORE 34 RESET 33 COUNT 32 COUNT INHIBIT 31 LZB OUT 30 LZB IN 29 CARRY 28
1/ DIGIT 27 2
200pF
4 5 BP 6 7 8 9 10 11 12
(BLANK)
FIGURE 7. SEGMENT ASSIGNMENT AND DISPLAY FONT
200pF
13 14 15 16 17 18 19 20
26 25 24 23 22 21
200pF EACH SEGMENT TO BACKPLANE WITH 200pF CAPACITOR
FIGURE 6. TEST CIRCUIT
6
ICM7224
HIGH ORDER DIGITS 1 OVERFLOW
LOW ORDER DIGITS 8-DIGIT LCD DISPLAY WITH OVERFLOW 4 SEG
6 SEG 15 SEG
3 SEG 4 SEG 6 SEG
1 BACKPLANE 15 SEG 3 SEG
SWITCH CLOSED INHIBITS LEADING ZERO BLANKING
20 10k
ICM7224 HIGH ORDER DIGITS SLAVE BACKPLANE
OSC 5 BP VSS STORE RESET COUNT COUNT INHIBIT LZB OUT LZB IN CARRY
1 VDD
20
ICM7224 LOW ORDER DIGITS MASTER BACKPLANE
OSC 5 BP VSS STORE RESET COUNT COUNT INHIBIT LZB OUT LZB IN CARRY
1 VDD
VDD
3V - 6V + -
COUT
21 1 2 3 4 5 6 7 CIN
36 35 34 33 32 31 30 29 28 27 14 13 12 11 10 9 8 ICM7207A
SWITCH OPEN 1s GATING SWITCH CLOSED 0.1s GATING CRYSTAL CIN = 22pF COUT = 22pF fO = 5.24288MHz RS < 75 CS = 0.015pF CP = 3.5pF
FIGURE 8. EIGHT-DIGIT PRECISION FREQUENCY COUNTER
40
21
1/ CD4069C 4
36 35 34 33 32 31 30 29 28 27 INPUT SIGNAL CONDITIONING (PRESCALER LEVEL SHIFTING)
INPUT SIGNAL
40
7

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